Phase-change material memory cell

ABSTRACT

A memory cell includes a current-steering device, a phase-change material disposed thereover, and a heating element and/or a cooling element.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of, and incorporatesherein by reference in its entirety, U.S. Provisional Patent ApplicationNo. 61/106,420, which was filed on Oct. 17, 2008.

TECHNICAL FIELD

In various embodiments, the present invention relates to phase-changememory cells, and more particularly to the formation of heating andcooling elements in conjunction with a phase-change memory cell.

BACKGROUND

Phase-change memory cells store information via changes in theirresistivity characteristics. This is accomplished by, e.g., melting aphase-change material (PCM) such as Ge₂Sb₂Te₅ (GST), and then eitherrapidly cooling the material so as to leave that material in anamorphous, high-resistive state or slowly cooling the material so as toleave it in a crystalline, low-resistive state. Each material statecorresponds to a different binary (zero or one) data value.

SUMMARY

Embodiments of the present invention include methods for forming aphase-change memory cell for improved heating and cooling by forming anintegral heating element and an integral cooling element. The heatingmechanism may be implemented by implanting one or more elemental speciesin the material on which the PCM is positioned, which may be combinedwith a technique for confining the PCM to a smaller volume in the areaof heating. The cooling mechanism may be implemented by minimizing thevolume of the PCM to be cooled and providing a metal (e.g., tungsten)heat sink on top that also acts as an etch stop during formation of theupper contact.

In an aspect, embodiments of the invention feature a memory cellincluding or consisting essentially of a current-steering device, aphase-change material disposed over the current-steering device, and,disposed between the current-steering device and the phase-changematerial, an element for increasing heat transfer to the phase-changematerial upon application of a voltage to the memory cell. Thecurrent-steering device, the phase-change material, and the elementcooperate to store data. Application of a voltage across thecurrent-steering device results in heating of the phase-change material,and, depending on its cooling rate, the phase-change material acquireseither a polycrystalline or an amorphous material state, each materialstate corresponding to a different binary (zero or one) data value.

The element may include or consist essentially of a layer having aresistance larger than the resistance of at least a portion of thecurrent-steering device. The element may include one or more implantedelemental species, e.g., oxygen, nitrogen, and/or germanium. Thecurrent-steering device may include or consist essentially of a diode.The phase-change material may include or consist essentially of an alloyof germanium, antimony, and tellurium.

In another aspect, embodiments of the invention feature a method offorming a memory cell. A current-steering device is provided, as is aphase-change material thereover. An element for increasing heat transferto the phase-change material upon application of a voltage to the memorycell is provided between the current-steering device and thephase-change material. The element may be provided by ion implantationof at least one elemental species. The elemental species may include orconsist essentially of oxygen, nitrogen, and/or germanium.

In yet another aspect, embodiments of the invention feature a memorycell including or consisting essentially of a current-steering device, acooling element disposed over the current-steering device, and aphase-change material disposed over the current-steering device andaround at least a portion of the cooling element. The cooling elementmay include or consist essentially of a material having a higher thermalconductivity than the thermal conductivity of the phase-change material.The cooling element may include or consist essentially of anon-phase-change material, e.g., tungsten or diamond.

In a further aspect, embodiments of the invention feature a method offorming a memory cell. A current-steering device is provided. A volumeof phase-change material disposed around a core region is provided overthe current-steering device, and a cooling element is provided withinthe core region. The cooling element may include or consist essentiallyof a material having a higher thermal conductivity than the thermalconductivity of the phase-change material. The cooling element mayinclude or consist essentially of a non-phase-change material, e.g.,tungsten or diamond.

In another aspect, embodiments of the invention feature a memory cellincluding or consisting essentially of a current-steering device, afirst phase-change material disposed over the current-steering device, afirst breakdown layer disposed between the current-steering device andthe first phase-change material, a second phase-change material disposedover the first phase-change material, and a second breakdown layerdisposed between the first phase-change material and the secondphase-change material. The first and/or the second breakdown layer mayinclude or consist essentially of a dielectric material. The firstand/or the second breakdown layer may include a breach therethrough. Thefirst and second phase-change materials may be different.

In yet another aspect, embodiments of the invention feature a method offorming a memory cell. A current-steering device is provided, as is afirst phase-change material thereover. A first breakdown layer isprovided between the current-steering device and the first phase-changematerial. A second phase-change material is provided over the firstphase-change material, and a second breakdown layer is provided betweenthe first phase-change material and the second phase-change material. Afirst breach may be formed in the first breakdown layer by applying avoltage across the first breakdown layer. A second breach may be formedin the second breakdown layer by applying a voltage across the secondbreakdown layer.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, like reference characters generally refer to the sameparts throughout the different views. Also, the drawings are notnecessarily to scale, emphasis instead generally being placed uponillustrating the principles of the invention. In the followingdescription, various embodiments of the present invention are describedwith reference to the following drawing, in which:

FIG. 1 illustrates a PCM memory cell according to embodiments of thepresent invention;

FIG. 2 illustrates a PCM memory cell according to embodiments of thepresent invention in which the heating within the PCM material isfurther constrained;

FIG. 3 illustrates a PCM memory cell according to embodiments of thepresent invention in which the heating within the PCM material isfurther constrained following initial breakdown of the lower breakdownlayer; and

FIG. 4 illustrates a PCM memory cell according to embodiments of thepresent invention in which the heating within the PCM material isfurther constrained following secondary breakdown of the upper breakdownlayer.

DETAILED DESCRIPTION

The process for fabricating deposited-material diodes on a siliconsubstrate is well known to those skilled in the art. Generally speakingand referencing FIG. 1, substrate 100 may be patterned with conductiverows 101 with a damascene process (or by patterning and etching) on topof which a current-steering device such as a diode 103 is fabricated.This diode 103 may be formed by depositing polysilicon that may be dopedin situ or implanted; in one embodiment, N+ polysilicon 104 isdeposited, followed by undoped polysilicon 105, the top portion of whichis then implanted with p-type dopants to form p-type region 106. Thestack may be then patterned and etched into a pillar shape wherever adiode is desired on row 101 or other bottom conductors (not shown). Inthe present examplary description, we assume the pillars areapproximately 90 nm across, although other sizes and geometries arewithin the scope of the present invention. The resulting pillars may beblanket-filled around with a dielectric material 102 such as siliconoxide (SiO₂), and this may be polished to expose the tops of thepolysilicon pillars. Next, about 80 nm of the polysilicon may be etchedback by an etchant that is selective to remove the polysilicon asopposed to the dielectric material 102 (many etches are known to thoseskilled in the art that will etch polysilicon faster than SiO₂) leavinga “cup” on top of the diode. Note that the thickness of the p-typeregion 106 may allow for the partial removal of this layer to allow p⁺polysilicon to remain following cup formation. The polysilicon stack maybe annealed, at any point after any the implant steps through cupformation, to improve the conductivity of the polysilicon and toactivate the dopant materials as is understood by those skilled in theart.

An approximately 50 Angstrom (Å) barrier liner layer of titanium (Ti)followed by approximately 100 Å of titanium nitride (TiN) may bedeposited followed by an approximately 20-second rapid thermal anneal(RTA) at approximately 670° C. to form a metal-semiconductor alloy(e.g., a silicide). Tungsten (and/or any one or more other metals)contact material may be deposited over substrate 100, which may then bepolished (e.g., by chemical-mechanical polishing (CMP)) to leave thecups filled with metal contact plugs. At this point, those diodes onwhich the phase-change cells are not to be formed may be patterned andmasked such that the tungsten may be etched away (e.g., by peroxide wetetch which will stop on the TiN liner) above the diodes that willreceive PCM material.

In one embodiment, dielectric layer 108 (i.e., a layer including orconsisting essentially of a dielectric material such as silicon nitride)is next deposited conformally to build a sidewall spacer about 28 nmthick. This may be then etched back to remove the dielectric layer 108on the wafer surface and at the bottom of the cups to leave the sidewallspacer in place (this is well understood by those skilled in the art,particularly by those skilled in the art of MOS transistor gateformation for those gates formed with sidewall spacers). Next, abreakdown layer 109 (i.e., a layer including or consisting essentiallyof a dielectric material such as SiO₂) may be deposited either by atomiclayer deposition (ALD) or by sputtering (or other depositiontechniques). The cup may then be filled by a blanket deposition (e.g.,by sputtering) of the PCM material 110 (e.g., a layer including orconsisting essentially of GST) and this film may be polished (e.g., byCMP with a tungsten polish) to remove all of the PCM material 110 exceptthat within the cups. A top contact 112 may be formed by depositing,e.g., a thin layer of amorphous carbon as a barrier layer to the GST inthe cups followed by top metal deposition, which is then patterned andetched to remove exposed top metal (and exposed amorphous carbon).

In one embodiment of the present invention, a heating element is addedto the memory cell. To form a heating element to contact the PCM, ashallow I² implant 107 of an elemental species such as oxygen, nitrogen,and/or germanium may be performed to increase the resistance at thediode-PCM junction; that is to say just at the top of the diode 103where it is closest to the PCM 110. In this way, the PCM may be heatedmore effectively when the storage location is to be altered (i.e., datais to be written).

In another embodiment of the present invention, an improved coolingelement is added to the memory cell. At the point of GST deposition, theGST film may be deposited conformally, but this film may be made thin soas to not fill the volume of the cups. The remainder of the cup volumemay be filled with a material 111 that is known to be a good conductorof heat. When the GST film is polished, a center core of theheat-conductive material 111 may remain in the center of the cupsurrounded by the GST layer. In this way, heat from the GST volume maybe better drawn away and into the top contact 112 where it will bedissipated. This non-phase-change heat-conductive material may includeor consist essentially of tungsten, another metal, a dielectric, or aninsulator such as diamond, e.g., chemical-vapor deposited (CVD) diamond(in this latter case, the current path will be through the PCM materialsidewalls to the top conductor). In another embodiment, the core 111 isa conductor of higher resistivity and thereby helps the forming of thedouble BDL-confined GST regions. Furthermore, by reducing the volume ofthe GST material in this way, the heating, when it occurs, may beconcentrated in a smaller volume of GST material, limiting the volume ofmaterial that experiences the phase change. Limiting the volume of thePCM in this way may increase its switching speed.

In another embodiment of the present invention, as depicted in FIG. 2,the deposition of the PCM material is separated into two depositions110, 200 with a second breakdown layer 210 deposited in between. Thisenables the formation of an even thinner first deposited layer of PCMmaterial to further constrain the volume of PCM material to be heated.This approach will help to further constrain the volume of PCM materialand give more control over the heating and cooling of the PCM material.

Activation of the PCM memory cell depicted in FIG. 1 may be accomplishedby applying a voltage (e.g., in the forward voltage direction of thediode) across the top and bottom contacts such that the breakdown layer109 is breached (as is done with an antifuse and is known to thoseskilled in the art), thereby forming a filament and very small contactpoint to the bottom of the GST material. Activation of the PCM memorycell depicted in FIGS. 2 through 4 may be accomplished by applying avoltage (in the forward voltage direction of the diode) across the topand bottom contacts such that the dielectric layers are breached instages. In the first stage, as depicted in FIG. 3, the current path maybe along the sidewalls of the cup through the thin, first deposited PCMlayer 110; this current may cause a breach (as is done with an antifuseand is known to those skilled in the art) through the lower breakdownlayer 109, thereby forming a filament 300 (and, hence, a very smallcontact point to the bottom of the GST material). The PCM material maybe heated and melted in the vicinity of the breach and the current maybe ramped down such that an area of low resistance is formed in the PCMmaterial at that area. In the second stage, as depicted in FIG. 4, asecond voltage may be applied to create a current path through the corePCM layer 200 (the “core”), causing a breach 400 to be formed throughthe second breakdown layer 210 to the area of low resistance PCMmaterial of the first PCM layer 110. The core PCM material 200 will beheated and melt in the vicinity of the breach of the second depositedbreakdown layer and the current will be ramped down such that an area oflow resistance is formed in the core PCM material 200 at that area. Avariation on this latter structure may include making the core out of amaterial other than PCM material 200 to vary the amount of coolingfollowing melting, but still resulting in a very small volume of PCMmaterial that will be melted during programming or erasing the storageelement PCM between the two breakdown layer breaches.

Memory devices incorporating embodiments of the present invention may beapplied to memory devices and systems for storing digital text, digitalbooks, digital music (such as MP3 players and cellular telephones),digital audio, digital photographs (wherein one or more digital stillimages may be stored including sequences of digital images), digitalvideo (such as personal entertainment devices), digital cartography(wherein one or more digital maps can be stored, such as GPS devices),and any other digital or digitized information as well as anycombinations thereof. Devices incorporating embodiments of the presentinvention may be embedded or removable, and may be interchangeable amongother devices that can access the data therein. Embodiments of theinvention may be packaged in any variety of industry-standard formfactor, including Compact Flash, Secure Digital, MultiMedia Cards,PCMCIA Cards, Memory Stick, any of a large variety of integrated circuitpackages including Ball Grid Arrays, Dual In-Line Packages (DIPs),SOICs, PLCC, TQFPs and the like, as well as in proprietary form factorsand custom designed packages. These packages may contain just the memorychip, multiple memory chips, one or more memory chips along with otherlogic devices or other storage devices such as PLDs, PLAs,micro-controllers, microprocessors, controller chips or chip-sets orother custom or standard circuitry.

The terms and expressions employed herein are used as terms andexpressions of description and not of limitation, and there is nointention, in the use of such terms and expressions, of excluding anyequivalents of the features shown and described or portions thereof. Inaddition, having described certain embodiments of the invention, it willbe apparent to those of ordinary skill in the art that other embodimentsincorporating the concepts disclosed herein may be used withoutdeparting from the spirit and scope of the invention. Accordingly, thedescribed embodiments are to be considered in all respects as onlyillustrative and not restrictive.

1. A memory cell comprising: a current-steering device; a phase-changematerial disposed over the current-steering device; and disposed betweenthe current-steering device and the phase-change material, an elementfor increasing heat transfer to the phase-change material uponapplication of a voltage to the memory cell.
 2. The memory cell of claim1, wherein the element comprises a layer having a resistance larger thana resistance of at least a portion of the current-steering device. 3.The memory cell of claim 1, wherein the element comprises an implantedelemental species selected from the group consisting of: oxygen,nitrogen, and germanium.
 4. The memory cell of claim 1, wherein thecurrent-steering device comprises a diode.
 5. The memory cell of claim1, wherein the phase-change material comprises an alloy of germanium,antimony, and tellurium.
 6. A method of forming a memory cell, themethod comprising: providing a current-steering device; providing aphase-change material over the current-steering device; and providing,between the current-steering device and the phase-change material, anelement for increasing heat transfer to the phase-change material uponapplication of a voltage to the memory cell.
 7. The method of claim 6,wherein the element is provided by ion implantation of at least oneelemental species.
 8. The method of claim 7, wherein the at least oneelemental species comprises at least one of oxygen, nitrogen, orgermanium.
 9. A memory cell comprising: a current-steering device; acooling element disposed over the current-steering device; and aphase-change material disposed over the current-steering device andaround at least a portion of the cooling element.
 10. The memory cell ofclaim 9, wherein the cooling element comprises a material having ahigher thermal conductivity than a thermal conductivity of thephase-change material.
 11. The memory cell of claim 9, wherein thecooling element comprises a non-phase-change material.
 12. The memorycell of claim 11, wherein the cooling element comprises tungsten. 13.The memory cell of claim 11, wherein the cooling element comprisesdiamond.
 14. A method of forming a memory cell, the method comprising:providing a current-steering device; providing over the current-steeringdevice a volume of phase-change material disposed around a core region;and providing a cooling element within the core region.
 15. The methodof claim 14, wherein the cooling element comprises a material having ahigher thermal conductivity than a thermal conductivity of thephase-change material.
 16. The method of claim 14, wherein the coolingelement comprises a non-phase-change material.
 17. The method of claim16, wherein the cooling element comprises tungsten.
 18. The method ofclaim 16, wherein the cooling element comprises diamond.
 19. A memorycell comprising: a current-steering device; a first phase-changematerial disposed over the current-steering device; a first breakdownlayer disposed between the current-steering device and the firstphase-change material; a second phase-change material disposed over thefirst phase-change material; and a second breakdown layer disposedbetween the first phase-change material and the second phase-changematerial.
 20. The memory cell of claim 19, wherein the first and secondbreakdown layers each comprise a dielectric material.
 21. The memorycell of claim 19, wherein the first and second breakdown layers eachcomprise a breach therethrough.
 22. The memory cell of claim 19, whereinthe first and second phase-change materials are different.
 23. A methodof forming a memory cell, the method comprising: providing acurrent-steering device; providing a first phase-change material overthe current-steering device; providing a first breakdown layer betweenthe current-steering device and the first phase-change material;providing a second phase-change material over the first phase-changematerial; and providing a second breakdown layer between the firstphase-change material and the second phase-change material.
 24. Themethod of claim 23, further comprising forming a first breach in thefirst breakdown layer by applying a voltage across the first breakdownlayer.
 25. The method of claim 24, further comprising forming a secondbreach in the second breakdown layer by applying a voltage across thesecond breakdown layer.